There are lots of constraints on the design of augmented-reality techniques. Not the least of which is that “you must look presentable while you’re strolling round,” Meta analysis scientist Tony Wu instructed engineers Tuesday on the IEEE International Solid State Circuits Conference (ISSCC). “You may’t have a shoebox in your face on a regular basis.”
An AR system additionally have to be light-weight and might’t throw off a whole lot of warmth. And it must be miserly with energy as a result of no one desires to need to recharge wearable electronics each couple of hours. Then once more, when you’ve received a flaming-hot shoebox in your face, you would possibly be glad about a brief battery life.
The 3D chip may observe two arms concurrently utilizing 40 % much less power than a single die may do with just one hand. What’s extra, it did so 40 % sooner.
Wu is a part of the Meta staff engaged on the silicon smarts to make an AR system, called Aria, that’s as little like a scorching shoebox as they’ll make it. An enormous a part of the answer, Wu instructed engineers, is 3D chip integration technology. At ISSCC, Meta detailed how the corporate’s prototype AR processor makes use of 3D to do extra in the identical space and with the identical quantity or much less power.
Meta’s prototype chip has each logic and reminiscence on every silicon die. They’re bonded face-to-face, and through-silicon vias carry information and energy to each.Meta
The prototype chip is 2 ICs of equal measurement—4.1 by 3.7 millimeters. They’re bonded collectively in a course of referred to as face-to-face wafer-to-wafer hybrid bonding. Because the title implies, it entails flipping two totally processed wafers in order that they’re dealing with one another and bonding them so their interconnects hyperlink collectively instantly. (The “hybrid bonding” half means it’s a direct copper-to-copper connection. No solder wanted.)
The TSMC technology used for this meant the 2 items of silicon may kind a vertical connection roughly each 2 micrometers. The prototype didn’t totally make use of this density: It required round 33,000 sign connections between the 2 items of silicon and 6 million energy connections. The underside die makes use of through-silicon vias (TSVs)—vertical connections bored down via the silicon—to get alerts out of the chip and energy in.
3D stacking meant the staff may enhance the chip’s computing energy—letting it deal with larger duties—with out including to its measurement. The chip’s machine-learning unit has 4 compute cores on the underside die and 1 megabyte of native reminiscence, however the prime die provides one other 3 MB, accessible via 27,000 vertical information channels on the similar velocity and power—0.15 picojoules per byte— as in the event that they had been one large piece of silicon.
The staff examined the chip on a machine-learning process essential for augmented actuality, hand monitoring. The 3D chip was capable of observe two arms concurrently utilizing 40 % much less power than a single die may do with just one hand. What’s extra, it did so 40 % sooner.
Along with machine studying, the chip can do image-processing duties. 3D made a giant distinction right here, once more. Whereas the 2D model was restricted to compressed photos, the 3D chip can do full HD utilizing the identical quantity of power.
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